HBM3 interface provides full support for the HBM3 interface, compatible with draft JEDEC specification version 1.02 and DFI-version 4.0 or 5.0 specification Compliant. Through its HBM3 compatibility, it provides a simple interface to a wide range of low-cost devices. HBM3 IIP is proven in FPGA environment. The host interface of the HBM3 can be simple interface or can be AMBA AHB, AMBA AHB-Lite, AMBA APB, AMBA AXI, AMBA AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or Custom protocol.
HBM3 Controller IIP is supported natively in Verilog and VHDL
- Features
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- Supports HBM3 protocol standard draft JEDEC specification version 1.02.
- Compliant with DFI version 4.0 or 5.0 Specification.
- Supports up to 16 AXI ports with data width upto 512 bits.
- Supports controllable outstanding transactions for AXI write and read channels
- Supports in port arbitration and multi port arbitration.
- Supports user programmable page policy.
- Closed page policy
- Open page policy
- Supports Error Checking and correction (ECC).
- Supports retry on ECC error, with retry limit user controllable.
- Supports high clock speeds in ASIC and FPGA.
- Supports low latency for write and read path.
- Supports reordering of transactions for higher performance.
- Supports all the HBM3 commands as per the specs.
- Supports programmable clock frequency of operation.
- Supports burst length of 8.
- Supports programmable READ/WRITE Latency timings.
- Supports Bank grouping.
- Supports all Interface Groups.
- Supports DRAM Clock disabling feature.
- Supports Low power control features.
- Supports 64 banks per pseudo channel.
- Supports 1:4, 1:2 and 1:1 MC to PHY frequency ratio.
- Supports 16, 32 or 48 banks per channel based on device density and channel.
- Supports 2KB page size per channel.
- Supports semi-independent row and column command interfaces.
- Supports up to 16 channels per stack.
- Supports WDQS-to-CK training.
- Supports all Mode registers programming.
- Supports Data Bus Inversion (DBIac) for write and read.
- Supports Pseudo Channel Mode Operation (32 DQ width for Pseudo Channel Mode).
- Supports 2 Pseudo channels per channel.
- Supports Self-Refresh Modes.
- Supports channel density of 2 GB to 32 GB.
- Supports 64 DQ width and Optional ECC pin support/channel.
- Supports ECC.
- Supports Error signaling.
- Supports write data mask and data strobe features.
- Supports for power down features.
- Supports DFI Read/Write Chip Select.
- Supports for input clock stop and frequency change.
- Fully synthesizable
- Static synchronous design.
- Positive edge clocking and no internal tri-states.
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
- Build in self test to test all locations in memory to identify damaged locations
- Benefits
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- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's HBM3 IP contains following
- The HBM3 interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases.
- Lint, CDC, Synthesis, Simulation Scripts with waiver files.
- IP-XACT RDL generated address map.
- Firmware code and Linux driver package.
- Documentation contains User's Guide and Release notes.
