RapidIO Synthesizable Transactor provides a smart way to verify the RapidIO bi-directional two-wire bus. RapidIO Synthesizable Transactor provides a smart way to verify the RapidIO component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's RapidIO Synthesizable Transactor is compliant with RapidIO Trade Association, RapidIO Interconnect Specification version 1.3, 2.0, 2.1, 2.3, 3.0, 3.1, 3.2 and 4.0. RapidIO VIP is implemented in a layered fashion. Whichis basically divided into a physical layer, transport layer and logical layer.
- Features
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- Supports RapidIO specification 1.3, 2.0, 2.1, 2.2, 3.0, 3.1, 3.2, 4.0 and 4.1.
- Supports Serial 1x/2x/4x/8x and 16x Physical lanes.
- Supports 25.78125Gbaud/s, 12.5Gbaud/s, 10.3125Gbaud/s, 6.25Gbaud/s, 5Gbaud/s,3.125 Gbaud/s, 2.5 Gbaud/s, 1.25 Gbaud/s.
- 8b/10b Encode and Decode functions.
- 64b/67b Encode and Decode functions.
- Supports scrambler/Descrambler.
- 66, 50, or 34-bit addressing on the RapidIO interface.
- Supports Parallel Physical 8/16 bits interfaces.
- Supports all types of packets and sizes.
- Supports all types of IDLE sequences, Control and Status Symbols.
- Supports 8-bit, 16-bit and 32-bit device IDs.
- Automatic freeing of resources used by acknowledged packets.
- Supports I/O system, message passing and globally shared distributed memory (GSM).
- Supports communication with mailboxes via messages.
- Supports generation and reaction to flow control.
- Supports out of order transaction delivery based on the prioritization.
- Supports critical request flow ordering.
- Very flexible to insert errors in serial lanes.
- Supports Error Management Extensions.
- Provides error injection and error detection with a wide variety of error types. Which includes,
- Under and oversize packet.
- CRC errors.
- Invalid code group insertion.
- Invalid /K/ characters insertion.
- Lane Skew insertion.
- Error on control symbol.
- Unsupported packet types.
- Supports cancellation and retrying of packets mechanisms.
- Support all types of timing and protocol violation detection.
- Status counters to keep track of various events.Which includes
- Corrupted/uncorrupted packets.
- Corrupted/uncorrupted control symbols.
- Type of packet.
- CRC error.
- Total number of errors detected.
- Rapidio verification IP comes with complete testsuite to test every feature of Rapidio spec and also as per RIO LAB testsuite.
- Notifies the testbench of significant events such as transactions, warnings, timing and Protocol violations.
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- RapidIO Synthesizable Transactor Env
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SmartDV's RapidIO Synthesizable env contains following:
- Synthesizable transactors
- Complete regression suite containing all the RapidIO testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation contains User's Guide and Release notes
