DMX Verification IP provides a smart way to verify the DMX component of SOC or ASIC. The SmartDV's DMX Verification IP is fully compliant with standard DMX American National Standard E1.11 - 2008 (R2013) Specification and provides the following features.
DMX Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
DMX Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Transmit and receive commands allow the user to transmit and receive DMX512 packets
- Fully configurable serial interface
- Supports programmable clock frequency of operation.
- Configurable baud rate
- Supports the reset sequence
- Supports all reserved alternative start codes
- Supports up to maximum of 513 slots
- Supports ASCII Text character set encoding technique
- Supports UTF-8 Text character set encoding technique
- Supports all types of error insertion and detection
- Minimum break length error
- Maximum break length error
- Invalid start code error
- Maximum mark before break error
- Minimum mark after break error
- Maximum mark after break error
- Break to break timeout errors
- DMX512 packet timeout errors
- Start bit error
- Stop bit error
- 16-Bits checksum error
- 8-Bits checksum error
- Wrong SIP sequence number error
- Timeout errors
- Glitch insertion and detection
- Monitors, detects and notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
- Allows creation of both random and directed testcases as well as constraints randomization.
- Status counters for various events on bus.
- Supports callbacks in monitor, receiver and transmitter BFMs for user processing of data.
- DMX Verification IP comes with complete testsuite to test every feature of DMX specification.
- Functional coverage for complete DMX ANSI E1.11 - 2008 features.
- Benefits
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- Faster testbench development and more complete verification of DMX designs.
- Easy to use command interface simplifies testbench control and configuration of TX and RX.
- Simplifies results analysis.
- Runs in every major simulation environment.
- DMX Verification Env
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SmartDV's DMX Verification env contains following.
- Complete regression suite containing all the DMX testcases.
- Examples showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation contains User's Guide and Release notes.
