AMBA AXI4-Lite Verification IP provides an smart way to verify the ARM AMBA AXI4-Lite component of a SOC or a ASIC. The SmartDV's AMBA AXI4-Lite Verification IP is fully compliant with standard AMBA AXI4-Lite Specification. Our AMBA AXI4-Lite VIP is proved across multiple customers.
AMBA AXI4-Lite Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
AMBA AXI4-Lite Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Compliant with the latest ARM AMBA AXI4-Lite Protocol Specification.
- Supports AXI4-Lite Master, Slave, Monitor and Checker.
- Supports all ARM AMBA AXI4-Lite data and address widths.
- Supports all protocol transfer types and response types.
- Supports constrained randomization of protocol attributes.
- Separate address/control, data and response phases. Separate read and write channels.
- Slave supports fine grain control of response per address or per transaction.
- Programmable wait states or delay insertion on different channels.
- Ability to inject errors during data transfer.
- Write strobe support to enable sparse data transfer on the write data bus.
- Unaligned address access support.
- Ability to issue multiple outstanding transactions.
- Out of order transaction completion support.
- Protected accesses with normal/privileged,secure/non-secure and data/instruction
- Ability to configure the width of all signals.
- Support for bus inactivity detection and timeout.
- Configurable WID signal enable support.
- Burst length of 1.
- Write strobe support.
- Data bus width of 32-bit or 64-bit.
- Quality of Service signaling.
- Multiple region interfaces.
- User signaling support.
- Ability to break longer bursts into multiple shorter bursts
- Supports unmapped region address accesses
- AWCACHE and ARCACHE Attributes.
- Low-power Interface support
- Programmable Timeout insertion.
- Supports FIFO memory.
- Rich set of configuration parameters to control AXI4-Lite functionality.
- On-the-fly protocol and data checking.
- Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
- Built in coverage analysis.
- Callbacks in Master, Slave and Monitor for various events.
- Status counters for various events on bus.
- AXI4-Lite Verification IP comes with complete testsuite to test every feature of ARM AMBA AXI4-Lite specification.
- Benefits
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- Faster testbench development and more complete verification of AMBA AXI4-Lite designs.
- Easy to use command interface simplifies testbench control and configuration of Master and Slave.
- Simplifies results analysis.
- Runs in every major simulation environment.
- AMBA AXI4-Lite Verification Env
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SmartDV's AMBA AXI4-Lite Verification env contains following.
- Complete regression suite containing all the AMBA AXI4-Lite testcases.
- Examples showing how to connect various components, and usage of BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
