ARINC 419 Synthesizable Transactor provides an smart way to verify the ARINC 419 component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's ARINC 419 Synthesizable Transactor is fully compliant with standard ARINC 419 Specification and provides the following features.
- Features
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- Supports ARINC REPORT 419 - 3
- Supports 32 bit words containing a 24 bit data portion containing the actual information, and an 8 bit label describing the data itself
- Supports transmission rates at 11 ± 3.5 kbps
- Supports bipolar Return-to-Zero encoding format
- Supports following data types
- Binary – BNR – Transmitted in fractional two’s complement notation
- Binary Coded Decimal – BCD – Numerical subset of ISO Alphabet No. 5
- Maintenance Data and Acknowledgement - Requires two-way communication
- Supports duplex or two-way communication in Maintenance Data and acknowledgement between source and sink
- Supports all types of error insertion/detections as given below:
- Parity Errors
- Word count errors
- Synchronization errors
- Invalid label Errors
- Supports FIFO depth programmable
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- ARINC 419 Synthesizable Env
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SmartDV's ARINC 419 Synthesizable env contains following:
- Synthesizable transactors
- Complete regression suite containing all the ARINC 419 testcases
- Examples showing how to connect and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation also contains User's Guide and Release notes
