AMBA LPI Assertion IP provides an efficient and smart way to verify the AMBA LPI designs quickly without a testbench. The SmartDV's AMBA LPI Assertion IP is fully compliant with standard AMBA LPI Specification.
AMBA LPI Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
AMBA LPI Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Specification Compliance
- Compliant to ARM AMBA LPI protocol
- Supports LPI Q-Channel and P-Channel signal level checks
- Assertion IP features
- Assertion IP includes:
- System Verilog assertions
- System Verilog assumptions
- System Verilog cover properties
- Synthesizable Verilog Auxiliary code
- Support Master mode, Slave mode, Monitor mode and Constraint mode.
- Supports Simulation mode (stimulus from SmartDV LPI VIP) and Formal mode (stimulus from Formal tool).
- Rich set of parameters to configure LPI Assertion IP functionality.
- Benefits
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- Runs in every major formal and simulation environment.
- AMBA LPI Assertion Env
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SmartDV's AMBA LPI Assertion env contains following.
- Detailed documentation of Assertion IP usage.
- Documentation also contains User's Guide and Release notes.
