JESD204C interface provides full support for the JESD204C synchronous serial interface,compatible with JESD204C version specification.Through its compatibility, it provides a simple interface to a wide range of low-cost devices. JESD204C Receiver IIP is proven in FPGA environment.The host interface of the JESD204C can be simple interface or can be AHB,AHB-Lite,APB,AXI,AXI-Lite,Tilelink,OCP,VCI,Avalon,PLB,Wishbone or Custom protocol.
JESD204C Receiver IIP is supported natively in Verilog and VHDL
- Features
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- Compliant with JESD204 specification JESD204A, JESD204B.01 and JESD204C.
- Full JESD204C receive functionality.
- Supports data rate upto 32 Gbps.
- Supports programmable clock frequency up to 32 GHz.
- Supports up to Subclass 0, 1, 2.
- Supports up to Version A, B and C.
- Supports 1 to 8 lanes.
- Supports 1 to 8 converters per receiver.
- Supports frame sizes of 1,2,4,8 and 16 octets per frame.
- Supports HD-mode.
- Supports 1 to 32 bit data width per converter.
- Supports CF = 0 and 1 control words per frame clock period per link.
- Supports 0 to 3 control bits per sample.
- Supports 1 to 8 samples per converter.
- Supports 1 to 32 frames per multiframe.
- Supports 4, 8, 12, 16, 20, 24, 28 and 32 bits per sample.
- Supports 0 to 15 bank ID – extension to DID.
- Supports 0 to 255 device identification number.
- Supports 0 to 7 lane identification number.
- Supports 10/8b decoding.
- Supports 66b/64b decoding.
- Supports 80b/64b decoding.
- Supports Forward Error Correction (FEC) and cyclic redundancy checks (CRC).
- Supports single block, Multi block and extended multi block.
- Supports reporting of various error statistics.
- Supports different Serdes interfaces 10,20,40,60 bits and custom bits per lane.
- Scrambler can be enabled or disabled.
- MCDA-ML (Multiple-Converter Device Alignment, Multiple-Lanes) device supported.
- Benefits
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- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs,license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's JESD204C Receiver IP contains following
- The JESD204C Receiver interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases.
- Lint, CDC, Synthesis, Simulation Scripts with waiver files.
- IP-XACT RDL generated address map.
- Firmware code and Linux driver package.
- Documentation contains User's Guide and Release notes.
