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USB3.x HOST IIP

USB3.x HOST IIP

USB3.x Host interface provides full support for the USB3.x synchronous serial interface, compatible with USB 3.0/3.1/3.2 specification. Through its USB compatibility, it provides a simple interface to a wide range of low-cost devices. USB3.x Host IIP is proven in FPGA environment. The host interface of the USB3.x Host can be simple interface or can be AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

USB3.x HOST IIP is supported natively in Verilog and VHDL

Features
  • USB 3.0/3.1/3.2 Common support
    • Compliant with USB 3.0/3.1/3.2 specification
    • Supports Superspeed USB 3.0, SuperSpeedPlus 3.1, 3.2 and 3.0 OTG
    • Configurable number of Configurations, Interfaces, Alternative Interfaces and Endpoints
    • Configurable PIPE Interface width 8, 16 or 32 bits
    • Supports Low frequency periodic signaling (LFPS) for initialization and power management(U1, U2 & U3)
    • Supports Interrupt/Bulk/Isochronous/Control Transfers
    • Control transfers supported by Endpoint 0
    • Separate Endpoint Buffers for IN bound and OUT bound packets
    • Supports lane polarity inversion
    • Supports Bulk Streaming
    • Supports extensible Host Controller Interface(xHCI)
    • Supports Scrambler/Descrambler
    • Option to enable/disable scrambling
    • CRC checking and generation
    • Supports Protocol Layer Error Handling.
    • Provides prioritized scheduling for periodic endpoints.
    • Separate round robin scheduling algorithm within Periodic and Non-periodic endpoints pipes.
    • Supports PTM
    • Implements Type 1 and 2 Buffers
    • Supports LFPS Signaling, SCD/LBPM Messaging
    • Supports Master and Slave Loopback mode for PHY layer testing
    • Supports Compliance mode entry as per specification.
    • Supports USB Suspend state and supports remote wakeup devices.
    • Supports all SS/SSP Link Power Management States – U1, U2, U3
    • Supports all HS/FS USB Link Power Management States – L1, L2.
    • Supports system low power and related system states such as Sleep, Hibernate, Warm/ Cold boot etc.
    • Support for clock gating and multi-power-well support.
    • This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262
  • USB 3.0
    • Supports Gen1 super speed with 5GT/s data rate
    • Supports single lane
    • Supports ADP,HNP,SRP and RSP
    • Supports LCRD_A to LCRD_D Credits
  • USB 3.1
  • In addition to USB3.0 features,USB3.1 supports the following features
    • Supports Gen2 with SuperSpeedPlus and Gen1 with Super speed
    • Supports specific LFPS patterns(SCD1/SCD2) for Super speed plus ports
    • Supports SuperSpeedPlus LFPS Based PWM Message (LBPM)
    • Supports SuperSpeedPlus Precision Time Measurement
    • Supports SuperSpeedPlus Transaction Reordering for periodic and asynchronous packet
    • Supports Length field replica
    • Supports Endpoint companion descriptor
    • Supports Type-A and Type-B credits
    • Supports 128B/132B Encoding/Decoding
  • USB 3.2
  • In addition to USB3.0 and USB3.1 features, USB 3.2 supports the following features.
    • Supports Dual lane
    • Supports Gen2 with SuperSpeedPlus and Gen1 with Super speed
    • Supports Deskew buffer
    • Supports Data striping in dual lanes
    • Supports Configuration summary descriptor
    • Supports link error count and soft error count
    • Supports retimer connectivity models
    • Supports all the Retimer state machine states[RTSM]
    • Supports SRIS and Bit-Level Retimers functionality
    • Supports Retimer presence announcement through LBPM
  • Support DMA (Optional)
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple interface allows easy connection to microprocessor/microcontroller devices.
Benefits
  • Single Site license option is provided to companies designing in a single site.
  • Multi Sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
Deliverables

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    SmartDV's USB3.x Host IP contains following

  • The USB3.x Host interface is available in Source and netlist products.
  • The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes.
  • ISO26262 Safety Manual (SAM) Document
  • ISO26262 Failure Modes, Effects and Diagnostics Analysis (FMEDA) Document

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