MIPI DEBUG Verification IP provides a smart way to verify the MIPI DEBUG bi-directional two-wire bus. The SmartDV's MIPI DEBUG Verification IP is fully compliant with MIPI DEBUG version 1.0 specification.
MIPI DEBUG Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
MIPI DEBUG Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Compliant with MIPI Debug version 1.0 specification.
- Full MIPI Debug functionality.
- Support full I3C Slave with CCC, Hot Join, IBI, DAA and HDR mode.
- Full Link and Network/Transport layer.
- Support Network adaptors for following
- Supports upto 16 Network Adaptors
- Supports error detection and recovery
- Callbacks in Master, Slave and Monitor for user processing of data.
- Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
- Functional coverage of complete MIPI DEBUG specs.
- MIPI DEBUG Verification IP comes with complete testsuite to test every feature of MIPI DEBUG specification.
- Supports Error Handling
- Benefits
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- Faster testbench development and more complete verification of MIPI DEBUG designs.
- Easy to use command interface simplifies testbench control and configuration of TX and RX.
- Simplifies results analysis.
- Runs in every major simulation environment.
- MIPI DEBUG Verification Env
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SmartDV's MIPI DEBUG Verification env contains following.
- Complete regression suite containing all the MIPI DEBUG testcases to certify MIPI DEBUG Slave/Master device
- Examples showing how to connect various components and usage of Master, Slave and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
