SDIO Synthesizable Transactor is compliant with SDIO 1.0/2.0/3.0/4.20/5.0/5.10/6.0/6.10/7.0/7.10/8.0 specifications and verifies SDIO. SDIO is build on top of it to make it robust. SDIO Synthesizable Transactor provides a smart way to verify the SDIO component of a SOC or a ASIC in Emulator or FPGA platform. SDIO Synthesizable Transactor is developed by experts in networking, who have developed networking products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a networking product.
- Features
-
- SDIO Specification 1.0/2.0/3.0/4.20/5.0/5.10/6.0/6.10/7.0/7.10/8.0(Draft) compliant.
- Supports SDIO, SD Memory, SD Combo card and Multi-media cards.
- Easily configurable to work as SDIO aware or non-SDIO aware Host controller.
- Card detection on DAT [3] line in SD mode and CS line in SPI mode.
- Re-initialization of combo card in either SDIO only mode or SD memory only mode.
- Command level features such as resetting the card, setting bus width and changing bus mode (SD to SPI).
- 1-bit, 4-bit, 8-bit SD bus mode and SPI bus mode.
- Supports read-write, read-only cards.
- All version 3.0/4.20/5.0/5.10/6.0/6.10/7.0/7.10/8.0(Draft) features supported such as speed class, tuning, voltage and block size control.
- Supports capacity of Memory.
- Switch function command supports Bus speed mode,command system,drive strength & future function.
- Set block count(CMD23) command is supported.
- Supports different memory capacities given below:
- Standard Capacity SD Memory Card (SDSC) : Up to 2 GB
- High Capacity SD Memory Card (SDHC) : More than 2GB and up to 32GB
- Extended Capacity SD Memory Card (SDXC) : More than 32GB and up to 2TB
- Ultra Capacity SD Memory Card (SDUC) : More than 2TB and up to 128TB
- All UHS1 modes – SDR50/SDR104/DDR50.
- Low speed mode, full speed mode and high speed mode operations.
- Single byte, single block, multiple block (finite and infinite) transfer operations.
- Direct command during data transfer (SD mode only).
- Read wait operation and allows read wait control by stopping clock and by asserting DAT [2] line low.
- Supports all features of SDIO card type-A specification for bluetooth version 1.00.
- Supports all features of SDIO card type-B specification for bluetooth version 1.00.
- Supports all features of SD specification Part1 eSD(Embedded SD) addendum version 2.10
- Supports all features of write protect feature.
- Supports application specific commands.
- Supports card ownership protection.
- Supports cache operation.
- Supports command queuing.
- Supports Card maintenance (background operations).
- Supports Low voltage 1.8V cards.
- Supports discard and Full user area logical erase.
- Asynchronous and synchronous abort mechanism.
- Supports function extension specification.
- Supports video speed class specification
- Suspend/Resume card operation.
- Lock-unlock and erase operation card features.
- SD 1-bit , SPI mode interrupt and SD 4-bit mode card interrupts.
- Clock disable and interrupt wake up card features.
- Tracking of the transmit and receive counters.
- Detects and reports the following errors.
- Out of range error
- Address misalign error
- CRC error
- Switch error
- Illegal command error
- Block length error
- Lock-unlock failed error
- Erase sequence error
- Direction bit error
- Stuff bit error
- Erase param error
- Parameter error
- Reserved bit error
- Invalid voltage error
- Function number error
- CSD/CID overwrite error
- WP violation error
- Protocol Checker fully compliant with SDIO Specification 1.0/2.0/3.0/4.20/5.0/5.10/6.0/6.10/7.0/7.10/8.0(Draft) compliant.
- Supports constraints randomization.
- Complete testsuite to verify each and every feature of SDIO standard.
- Supports Bus-accurate timing.
- Status counters for various events on bus.
- Benefits
-
- Compatible with testbench writing using SmartDV's VIP.
- All UVM sequences/testcases written with VIP can be reused.
- Runs in every major emulators environment.
- Runs in custom FPGA platforms.
- SDIO Synthesizable Transactor Env
-
SmartDV's SDIO Synthesizable env contains following:
- Synthesizable transactors.
- Complete regression suite containing all the SDIO testcases.
- Examples showing how to connect various components, and usage of Synthesizable Transactor.
- Detailed documentation of all DPI, class, task and functions used in verification env.
- Documentation contains User's Guide and Release notes.