MDRAM Memory Model provides an smart way to verify the MDRAM component of a SOC or a ASIC. The SmartDV's MDRAM memory model is fully compliant with standard MDRAM Specification and provides the following features. Better than Denali Memory Models.
MDRAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
MDRAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Supports MDRAM memory devices from all leading vendors.
- Supports 100% of MDRAM protocol standard.
- Supports all the MDRAM commands as per the specs.
- Supports 16Mbit x 16 organisation.
- Supports fully synchronous to positive clock edge.
- Supports upto 4 banks.
- Supports automatic and controlled precharge command.
- Supports data mask for byte control.
- Supports 8192 refresh cycles/64ms.
- Supports programmable latency.
- Supports auto refresh.
- Supports random column addresses every clk.
- Supports the following wrap sequence
- Supports the following burst length
- Supports power down and clock suspend mode.
- Supports very low self refresh current.
- Checks for following
- Check-points include power on, Initialization and power off rules,
- State based rules, Active Command rules,
- Read/Write Command rules etc.
- All timing violations.
- Quickly validates the implementation of the standard MDRAM specification.
- Constantly monitors MDRAM behavior during simulation.
- Protocol checker fully compliant with MDRAM Specification.
- Notifies the test bench of significant events such as transactions, warnings, timing.
- nd protocol violations.
- Built in functional coverage analysis.
- Supports Callbacks, so that user can access the data observed by monitor.
- Benefits
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- Faster testbench development and more complete verification of MDRAM designs.
- Easy to use command interface simplifies monitor control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
- MDRAM Verification Env
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SmartDV's MDRAM Verification env contains following.
- Complete regression suite containing all the MDRAM testcases.
- Complete UVM/OVM sequence library for MDRAM controller.
- Examples showing how to connect and usage of Model.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
