RLDRAM Synthesizable Transactor provides a smart way to verify the RLDRAM component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's RLDRAM Synthesizable Transactor is fully compliant with standard RLDRAM Specification and provides the following features.
- Features
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- Supports 100% of RLDRAM protocol standard
- Supports all the RLDRAM commands as per the specs
- Supports the following devices:
- Supports cyclic bank addressing for maximum data out bandwidth
- Supports non-multiplexed addresses
- Supports non-interruptible sequential burst of two (2-bit prefetch) and four (4-bit prefetch)
- Supports 600 Mb/s/p data rate
- Supports programmable read latency (RL) of 5-8
- Supports data valid signal (DVLD) activated as read data is available
- Supports data mask signals (DM0/DM1) to mask first and second part of write data burst
- Supports IEEE 1149.1 compliant JTAG boundary scan
- Supports internal auto precharge
- Supports programmable clock frequency of operation
- Supports all types of timing and protocol violation detection
- Models, detects and notifies the test bench of significant events such as transactions, warnings, timings and protocol violations
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- RLDRAM Synthesizable Transactor Env
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SmartDV's RLDRAM Synthesizable Transactor env contains following:
- Synthesizable transactors
- Complete regression suite containing all the RLDRAM testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes
