eSPI LPC Bridge interface is full-featured, easy-to-use, synthesizable design, compatible with Standard LPC Interface specification. Through its LPC compatibility, it provides a simple interface to a wide range of low-cost devices. eSPI LPC Bridge IIP is proven in FPGA environment.The host interface of the eSPI LPC Bridge can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
eSPI LPC Bridge IIP is supported natively in Verilog and VHDL
- Features
-
- Compliant with version 1.1 LPC Interface Specifications and eSPI base specification as defined in Enhanced Serial Peripheral Interface (eSPI) Specification rev.1.0
- Converts eSPI Peripheral Channel Transactions into LPC Memory write or read instructions
- Supports full LPC host capability
- Supports SOC Slave
- Supports monitoring of erroneous SOC transfers and reports error to the system
- Supports single, dual and quad eSPI data line
- Supports eSPI Slave (Enhanced Serial Peripheral Interface)
- Supports up to 66 MHz maximum operating frequency
- Supports Peripheral Channel
- Supports Virtual Wire Channel
- Supports following frames for eSPI:
- Put IO rd short
- Put IO wr short
- Put memrd32 short
- Put memwr32 short
- Put pc – Memory write 32
- Put pc – Memory read 32
- Get pc – Memory write 32
- Get pc – Memory read 32
- Put virtual wire
- Get virtual wire
- Supports LPC Master Interface
- Supports Serial IRQ Interface
- Support a variable number of wait-states
- Supports following frames for LPC:
- I/O write
- I/O read
- Memory write
- Memory read
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to microprocessor/microcontroller devices
- Benefits
-
- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IIP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
-
SmartDV's eSPI LPC Bridge IP contains following.
- The eSPI LPC Bridge interface is available in Source and netlist products.
- The Source product is delivered in verilog.If needed, VHDL and SystemC can also be provided
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and linux driver package
- Documentation contains User's Guide and Release notes.
