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PCI Express Verification IP

PCI Express Verification IP

PCIE Verification IP provides an smart way to verify the PCIE bi-directional bus. The SmartDV's PCIE Verification IP is fully compliant with version 1.0/2.0/3.0/4.0/5.0/6.0 of the PCIE Specification and provides the following features.

PCI Express Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env

PCI Express Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.

Features
  • Supports PCIE Express specs 1.0/2.0/3.0/4.0/5.0/6.0.
  • Supports mPCIE.
  • Supports PIPE, Serial, PCS/PMA, Low pin count and SerDes interface.
  • Supports MPHY RMMI and serial interface
  • - > All error injections in MPHY layer
  • - > All protocol checks for MPHY layer
  • - > All PWM and HS gears as supported by MPCIe
  • - > All lane configurations as supported by MPCIe
  • - > Automatic clock recovery for HS mode
  • - > Supports asymmetrical lane configuration
  • - > Supports dynamic bandwidth scalability as per specs
  • - > Supports both Rate A and Rate B
  • Supports UVM and Verilog APIs supplied , as well as C DPI exports
  • Supports for Gen 1,2,3,4,5 and 6 including SSC
  • Supports Full link speed and width negotiation up to 32 Lanes.
  • Supports Automated Error Injections at all layers.
  • Supports Checkers verify protocol timing checks and functional accuracy at each layer.
  • Supports Queuing for 8 VCs with configurable depth.
  • Supports Configurable TC to VC queue mapping.
  • Supports for multiple Requestor / Completer applications, including user supplied applications.
  • Supports User interface for direct TLP queuing and receipt.
  • Supports Checks all TLPs for correct formation of headers, prefixes, and ECRC.
  • Supports Full DL state machines.
  • Supports Checks all framing, LCRC, and lane rules.
  • Supports Check all DLLP fields and formatting.
  • Supports Interface to send / receive user defined DLLPs.
  • Supports ASPM and Software controlled Power Management.
  • Supports Automated Error Injections and checking.
  • Supports Full LTSSM state machine.
  • Supports SERDES model with digital clock recovery.
  • Supports Speed and Link Width negotiation.
  • Supports Upconfigure, polarity inversion, and lane-to-lane skew.
  • Supports Configurable Spread Spectrum Clocking (SSC).
  • Supports Gen 1 & 2 PCS, 8b/10b encoding.
  • Supports Gen 3, 4 & 5 128/130 encoding.
  • Supports Gen 6 flit based encoding.
  • Supports Configurable timers and timeouts.
  • Callbacks in Root complex,End point and monitor for user processing of data.
  • Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
  • PCI Express Verification IP comes with complete testsuite to test every feature of PCI Express specification.
  • Supports scoreboard checking
  • Built-in monitors for protocol checking, including a global bus monitor.
  • Functional coverage to cover all functionality of PCIE Root complex and End point.
  • Supports for multiple instantiations to create complex verification environment.
  • Supports for Scaled Flow control.
  • Supports for Data Link Feature Exchange.
  • Supports for Lane Margining at Receiver.
  • Supports for VF 10-Bit Tag Requester.
  • Supports for Enhanced Allocation.
  • Supports for Emergency Power Reduction State.
  • Supports Alternate Protocol Negotiation.
  • Supports Extended Speed Mode
  • Supports for Conventional PCI Advanced Features
  • Supports PAM4 encoding scheme
  • Supports Gray coding and Tx Precoding
  • Supports Flit mode and non flit mode
  • Supports Forward Error Correction mechanism
  • Supports L0p state
  • Supports Shared Credit Pool
  • Supports Link management DLLP
  • Compliant with PIPE 5.2.1 Specification
Benefits
  • Faster testbench development and more complete verification of PCI Express designs.
  • Easy to use command interface simplifies testbench control and configuration of Root complex and End point.
  • Simplifies results analysis.
  • Runs in every major simulation environment.
PCIE Verification Env

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    SmartDV's PCIE Verification env contains following.

  • Complete regression suite containing all the PCIE testcases to certify PCI Express Root complex and End point.
  • Examples showing how to connect various components, and usage of BFM and Monitor.
  • Detailed documentation of all class, task and function's used in verification env.
  • Documentation also contains User's Guide and Release notes.

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