AMBA CXS Assertion IP provides a smart way to verify the ARM AMBA CXS component of a SOC or a ASIC. The SmartDV's AMBA CXS Assertion IP is fully compliant with standard AMBA CXS Specification.
AMBA CXS Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
AMBA CXS Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Specification Compliance
- Compliant with the latest ARM AMBA CXS specification.
- Supports credit exchange mechanism.
- Supports Link activation and deactivation.
- Support for skipping link activation.
- Configurable credit mechanism including dynamic and pre-allocated credit control.
- Support for Interface properties and possible options as per protocol.
- Supports continuous delivery of data - uninterrupted transmission of packets.
- Fine grain control of below:
- Flit packets placement
- Packet control fields
- Ability to configure the width of all signals.
- Support for error injection during Link activation and deactivation.
- Programmable Protocol signal delays.
- Rich set of configuration parameters to control CXS functionality.
- Transaction logging and Performance Reporting support.
- Benefits
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- Runs in every major formal and simulation environment.
- AMBA CXS Assertion Env
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SmartDV's AMBA CXS Assertion env contains following.
- Detailed documentation of Assertion IP usage.
- Documentation also contains User's Guide and Release notes.
