DDR5 is full-featured, easy-to-use, synthesizable design, compatible with DDR5 JESD79-5 and JESD79-5 Rev1.40 (Draft) specification and DFI-version 5.0 Compliant. Through its DDR5 compatibility,it provides a simple interface to a wide range of low-cost devices. DDR5 IIP is proven in FPGA environment.The host interface of the DDR5 can be simple interface or can be AMBA AHB, AMBA AHB-Lite, AMBA APB, AMBA AXI, AMBA AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or Custom protocol.
DDR5 Controller IIP is supported natively in Verilog and VHDL
- Features
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- Supports DDR5 protocol standard JESD79-5 and JESD79-5 Rev1.40 (Draft) Specification.
- Compliant with DFI version 5.0 Specification.
- Supports up to 16 AXI ports with data width upto 512 bits.
- Supports controllable outstanding transactions for AXI write and read channels
- Supports in port arbitration and multi port arbitration.
- Supports user programmable page policy.
- Closed page policy
- Open page policy
- Supports Error Checking and correction (ECC).
- Supports retry on ECC error, with retry limit user controllable.
- Supports high clock speeds in ASIC and FPGA.
- Supports low latency for write and read path.
- Supports reordering of transactions for higher performance.
- Supports up to 64GB device density.
- Supports the following device types:
- Supports all speed grades as per specification.
- Supports for Mode Registers programming.
- Supports for Sequential burst type.
- Supports Programmable burst lengths of 8,16 and 32.
- Supports for Programmable Write and Read latency.
- Supports Multiple Outstanding transaction.
- Supports In-port Arbitration using QoS.
- Supports Write Pattern Comand.
- Supports Auto precharge for Write, Read and Write pattern command.
- Supports for Write Data Mask.
- Supports Refresh modes and Global refresh counter.
- Supports Refresh management all command.
- Supports Refresh management same bank command.
- Supports 2N mode.
- Supports CRC and ECC for Write and Read Operations.
- Supports for Self Refresh and Power Down operation.
- Supports for Precharge Command modes.
- Supports for Maximum Power Saving Mode (MPSM).
- Supports 1:4, 1:2 and 1:1 Controller to DFI PHY frequency ratio.
- Supports Programmable clock frequency operation.
- Fully synthesizable.
- Static synchronous design.
- Positive edge clocking and no internal tri-states.
- Scan test ready.
- Simple interface allows easy connection to Microprocessor/Microcontroller devices.
- Build in self test to test all locations in memory to identify damaged locations
- Benefits
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- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's DDR5 IP contains following
- The DDR5 interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases.
- Lint, CDC, Synthesis, Simulation Scripts with waiver files.
- IP-XACT RDL generated address map.
- Firmware code and Linux driver package.
- Documentation contains User's Guide and Release notes.
