HBM3 Assertion IP provides an efficient and smart way to verify the HBM3 designs quickly without a testbench. The SmartDV's HBM3 Assertion IP is fully compliant with standard HBM3 Specification.
HBM3 Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
HBM3 Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Specification Compliance
- Supports HBM3 memory devices from all leading vendors.
- Supports 100% of HBM3 protocol JEDEC draft specification version 1.1.
- Supports all the HBM3 commands as per the specs.
- Supports programmable clock frequency of operation.
- Support all types of timing and protocol violation detection.
- Supports burst length of 8.
- Supports programmable READ/WRITE Latency timings.
- Supports Bank grouping.
- Supports 2KB page size per channel.
- Supports 16,32 or 48 banks per channel based on device density and channel.
- Supports up to 16 channels per stack.
- Supports semi-independent row and column command interfaces.
- Supports WDQS-to-CK training.
- Checks for following
- Check-points include power on, Initialization and power off rules,
- State based rules, Active Command rules,
- Read/Write Commands rules etc.
- All timing violations.
- Supports all Mode registers programming.
- Supports DBIac write and read.
- Supports Pseudo Channel Mode Operation (32 DQ width for Pseudo Channel Mode).
- Supports 2 Pseudo channels per channel.
- Supports Self-Refresh Modes.
- Supports IEEE standard 1500.
- Supports channel density of 2 GB to 32 GB.
- Supports 64 DQ width + Optional ECC pin support/channel.
- Supports write data mask and data strobe features.
- Supports for power down features.
- Bus-accurate timing for min, max and typical values.
- Constantly monitors HBM3 behavior during simulation.
- Protocol checker fully compliant with HBM3 JEDEC draft specification version 1.1.
- Assertion IP features
- Assertion IP includes:
- System Verilog assertions
- System Verilog assumptions
- System Verilog cover properties
- Synthesizable Verilog Auxiliary code
- Support Master mode, Slave mode, Monitor mode and Constraint mode.
- Supports Simulation mode (stimulus from SmartDV HBM3 VIP) and Formal mode (stimulus from Formal tool).
- Rich set of parameters to configure HBM3 Assertion IP functionality.
- Benefits
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- Runs in every major formal and simulation environment.
- HBM3 Assertion Env
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SmartDV's HBM3 Assertion env contains following.
- Detailed documentation of Assertion IP usage.
- Documentation also contains User's Guide and Release notes.
