HBM Synthesizable Transactor provides a smart way to verify the HBM component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's HBM Synthesizable Transactor is fully compliant with standard HBM Specification and provides the following features.
- Features
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- Supports 100% of HBM protocol standard JESD235, JESD235A, JESD235B, JESD235C and JESD235D.
- Supports all the HBM commands as per the specs
- Supports all types of timing and protocol violation detection
- Supports burst length of 2 and 4
- Supports Programmable READ/WRITE Latency timings
- Supports Bank grouping
- Supports 8, 16, 32, 48 and 64 banks per channel
- Supports up to 8 channels per stack
- Supports Extended Addressing
- Supports Extended Write latency and Read latency
- Checks for following
- Check-points include power on, Initialization and power off rules
- State based rules, Active Command rules
- Read/Write Commands rules etc
- All timing violations
- Supports callbacks for user to get command data on bus
- Supports All Mode registers programming
- Supports DBIac write and read
- Supports Legacy Mode and Pseudo Channel Mode Operation (64 DQ width for Pseudo Channel Mode)
- Supports Self-Refresh Modes
- Supports channel density of 1 GB to 128 GB
- Supports 128 DQ width + Optional ECC pin support/channel
- Supports ECC
- Supports write data mask and data strobe features
- Supports for power down features
- Supports for input clock stop and frequency change
- Supports for target row refresh mode
- Supports for temperature compensated refresh reporting
- Supports for IEEE standard 1500
- Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- HBM Synthesizable Transactor Env
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SmartDV's HBM Synthesizable Transactor env contains following:
- Synthesizable transactors
- Complete regression suite containing all the HBM testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes
