DDR4 DB Memory Model provides an smart way to verify the DDR4 DB component of a SOC or a ASIC. The SmartDV's DDR4 DB memory model is fully compliant with DDR4 DB Standard of JESD82-32A and DDR4 Standard JESD79-4B and provides the following features. Better than Denali Models.
DDR4 DB Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
DDR4 DB Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Supports DDR4 DB devices from all leading vendors.
- Supports 100% of DDR4 DB protocol standard JESD82-32A and DDR4 Protocol standard JESD79-4B.
- Supports all the DDR4 DB commands as per the specs.
- Supports all speed grades as per specification.
- Supports Data buffer power down modes.
- Supports Dual frequency(Input clock frequency change).
- Supports for parity checking.
- Supports Command sequence error detection and error handling.
- Supports read commands and MPR override reads.
- Supports Per DRAM Addressability.
- Supports for BCW write and read commands.
- Supports for Function spaces(F0-F7).
- Supports Per Buffer Addressability.
- Supports for transparent mode.
- Supports following training modes
- DRAM Interface write leveling
- Host interface write leveling
- DRAM-to-DB Read delay(MRD) Training mode
- DB-to-DRAM Write Delay (MWD) Training Mode
- Host interface Read training
- Host interface Write training(HIW) mode
- Supports for optional NVDIMM feature.
- Quickly validates the implementation of the DDR4 DB standard JESD82-3A.
- Checks for following
- Check-points include power up initialization and power off rules
- State based rules, Active Command rules
- Read/Write Command rules etc.,
- Protocol checker fully compliant with DDR4 DB Specification JESD82-32A.
- Constantly monitors DDR4 DB behavior during simulation.
- Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
- Built in functional coverage analysis.
- Supports Callbacks, so that user can access the data observed by monitor.
- Benefits
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- Faster testbench development and more complete verification of DDR4 DB designs.
- Easy to use command interface simplifies monitor control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
- DDR4 DB Verification Env
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SmartDV's DDR4 DB Verification env contains following.
- Complete regression suite containing all the DDR4 DB testcases.
- Examples showing how to connect and usage of Model.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
