DDR Assertion IP provides an efficient and smart way to verify the DDR designs quickly without a testbench. The SmartDV's DDR Assertion IP is fully compliant with standard DDR Specification.
DDR Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
DDR Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
-
- Specification Compliance
- Quickly validates the implementation of the DDR standard
- Checks for following
- Check-points include power on, Initialization and power off rules,
- State based rules, Active Command rules,
- Read/Write Command rules etc.
- All timing violations.
- Constantly monitors DDR behavior.
- Supports every legal address and data width configurations.
- Supports every legal CAS latency.
- Supports mode register set command.
- Supports configurable auto refresh and self refresh mode.
- Supports all legal value of the auto precharge for each burst.
- Supports different burst lengths.
- Assertion IP features
- Assertion IP includes:
- System Verilog assertions
- System Verilog assumptions
- System Verilog cover properties
- Synthesizable Verilog Auxiliary code
- Support Master mode, Slave mode, Monitor mode and Constraint mode.
- Supports Simulation mode (stimulus from SmartDV DDR VIP) and Formal mode (stimulus from Formal tool).
- Rich set of parameters to configure DDR Assertion IP functionality.
- Benefits
-
- Runs in every major formal and simulation environment.
- DDR Assertion Env
-
SmartDV's DDR Assertion env contains following.
- Detailed documentation of Assertion IP usage.
- Documentation also contains User's Guide and Release notes.
