MHL Verification IP is fully compliant with MHL Specification version 1.0. It includes an extensive test suite covering most of the possible scenarios. It performs all possible protocol tests in a directed or a highly randomized fashion which adds the possibility to create the widest range of scenarios to verify the DUT effectively.
MHL Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
MHL Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Full MHL source and sink device functionality
- Supports Video data coding.
- Supports TERC4 coding and Control period codings.
- Supports Serialization and de-serialization.
- Supports three operating modes given below,
- Video period
- Data Island period
- Control period
- Supports Display Data Channel(DDC) operations over CBUS.
- Supports MHL Sideband Channel(MSC) operations over CBUS.
- Supports all video and data island packet formats in MHL Specification 1.0 compliant.
- Supports data island error correction(ECC).
- Supports High-bandwidth Digital Content Protection v1.4
- Supports CEA-861-E
- Supports Serial and Symbol interfaces
- Detects and reports the following errors.
- Invalid control character
- Invalid data character
- Invalid 10bit code
- Sync errors
- ECC errors
- Invalid packing injection and detection
- Protocol Checker fully compliant with MHL Specification 1.0 compliant.
- MHL Verification IP comes with complete testsuite to test every feature of MHL specification.
- Monitors, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations
- Status counters for various events on bus.
- Callbacks in transmitter, receiver for user processing of data.
- Functional coverage for complete MHL features.
- Benefits
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- Faster testbench development and more complete verification of MHL designs.
- Easy to use command interface simplifies testbench control and configuration of receiver and transmitter.
- Simplifies results analysis.
- Runs in every major simulation environment.
- MHL Verification Env
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SmartDV's MHL Verification env contains following.
- Complete regression suite containing all the MHL testcases.
- Examples showing how to connect various components, and usage of Transmitter, Receiver and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation contains User's Guide and Release notes.
