HyperFlash Memory Model provides an smart way to verify the HyperFlash component of a SOC or a ASIC. The SmartDV's HyperFlash memory model is fully compliant with Cypress HyperFlash Specification and provides the following features. Better than Denali Memory Models.
HyperFlash Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
HyperFlash Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Supports HyperFlash memory devices from all leading vendors.
- Supports 100% Cypress HyperFlash specification standard.
- Supports all the HyperFlash commands as per the specs.
- Supports 512 Mb Memory Density.
- Supports 8-bit data bus (DQ[7:0])
- Supports Read-Write Data Strobe (RWDS)
- Supports Double-Data Rate (DDR) - two data transfers per clock.
- Supports for Hardware reset.
- Checks for following
- Check-points include power up, initialization and power off rules
- State based rules
- All timing violations
- Supports Deep Power-Down
- Supports all types of timing and protocol violation detection.
- Constantly monitors HyperFlash behavior during simulation.
- Protocol checker fully compliant with Cypress HyperFlash Specification.
- Models, detects and notifies the test bench of significant events such as transactions,
- warnings, timing and protocol violations.
- Built in functional coverage analysis.
- Supports Callbacks, so that user can access the data observed by monitor.
- Benefits
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- Faster testbench development and more complete verification of HyperFlash designs.
- Easy to use command interface simplifies monitor control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
- HyperFlash Verification Env
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SmartDV's HyperFlash Verification env contains following.
- Complete regression suite containing all the HyperFlash testcases.
- Examples showing how to connect and usage of Model.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
