AMBA AXI4-Lite Synthesizable Transactor provides a smart way to verify the ARM AMBA AXI4-Lite component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's AMBA AXI4-Lite Synthesizable Transactor is fully compliant with standard AMBA AXI4-Lite Specification and provides the following features
- Features
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- Compliant with the latest ARM AMBA AXI4-Lite Protocol Specification.
- Supports AXI4-Lite Master and Slave.
- Supports all AXI4-Lite data and address widths.
- Supports all protocol transfer types and response types.
- Supports constrained randomization of protocol attributes.
- Separate address, data and response phases. Separate read and write channels.
- Slave supports fine grain control of response per address or per transaction.
- Programmable wait states or delay insertion on different channels.
- Ability to inject errors during data transfer.
- Write strobe support to enable sparse data transfer on the write data bus.
- Unaligned address access support.
- Ability to issue multiple outstanding transactions.
- Out of order transaction completion support.
- Protected accesses with normal/privileged, secure/non-secure and data/instruction
- Ability to configure the width of all signals.
- Support for bus inactivity detection and timeout.
- Configurable WID signal enable support.
- Burst length of 1.
- Write strobe support.
- Data bus width of 32-bit or 64-bit.
- Quality of Service signaling.
- Multiple region interfaces.
- User signaling support.
- Ability to break longer bursts into multiple shorter bursts
- Supports unmapped region address accesses
- AWCACHE and ARCACHE Attributes.
- Programmable Timeout insertion.
- Rich set of configuration parameters to control AXI4-Lite functionality.
- On-the-fly protocol and data checking.
- Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations.
- Callbacks in Master and Slave for various events.
- Status counters for various events on bus.
- Benefits
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- Compatible with testbench writing using SmartDV VIP's
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- AMBA AXI4-Lite Synthesizable Transactor Env
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SmartDV's AMBA AXI4-Lite Synthesizable env contains following:
- Synthesizable transactors
- Complete regression suite containing all the AMBA AXI4-Lite Synthesizable testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all class, task and functions used in verification env
- Documentation contains User's Guide and Release notes
