MIL STD 1773 Synthesizable Transactor provides a smart way to verify the MIL-STD-1773 component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV' MIL-STD-1773 Synthesizable Transactor is fully compliant with standard MIL-STD-1773 Specification and provides the following features.
- Features
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- Compliant with MIL STD 1773 Standard
- Supports Single/Dual/Quad channel, dual redundant bus communication modules
- Supports configurable length of word length, default 20 bits
- Supports configurable length of data bits, default 16
- Supports configurable message length per transfer
- Supports following encoding/decoding types
- NRZ coding
- Manchester II bi-phase coding
- Partial tri-level Manchester II bi-phase coding (i.e,PTMBC)
- Extended Manchester II bi-phase coding with beginning-stopping flags (i.e,EMBC-BSF)
- Supports single or multi bus control
- Supports following message formats
- Controller to terminal
- Terminal to controller
- Terminal to terminal
- Broadcast
- System control
- Supports upto 31 remote terminals
- Supports all types of errors insertion/detection as given below
- Command word sync error
- Data word sync error
- Status word sync error
- Command word parity error
- Data word parity error
- Status word parity error
- NRZ or Manchester encoding error
- Bi-phase encoding error
- Low bi-phase encoding error
- High bi-phase encoding error
- Oversize data word error
- Undersize data word error
- Extra data words error
- Less data words error
- Various illegal command errors
- Inter message gap error
- Terminal response timeout error
- Supports glitch insertion and detection
- Supports bus accurate timing and timing checks
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- MIL STD 1773 Synthesizable Env
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SmartDV's MIL STD 1773 Synthesizable env contains following:
- Synthesizable transactors
- Complete regression suite containing all the MIL STD 1773 testcases
- Examples showing how to connect and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation also contains User's Guide and Release notes
