TIMER is used to generate delays, signals with timing characteristics and measure the time between signal edges, compatible with standard protocol of TIMER specification. Through its TIMER compatibility, it provides a simple interface to a wide range of low-cost devices. TIMER IIP is proven in FPGA environment.The host interface of the TIMER can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite, AMBA AXI, AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
TIMER IIP is supported natively in Verilog and VHDL
- Features
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- Supports 32 timers each of 32 bit.
- Supports up/down counting modes.
- Supports configurable counter width.
- Supports to count a maximum value of 32'hFFFFFFFF in Generate and Capture mode.
- Supports to count a maximum value of 64'hFFFFFFFFFFFFFFFF in Cascade mode.
- Supports to generate a pulse after an interval.
- Supports to generate a square waveform.
- Supports to capture a value on trigger event.
- Supports automatically reloading value.
- Supports to hold count value.
- Supports PWM mode.
- Supports for halting and resuming timer.
- Supports cascaded mode of operation.
- Supports enabling and disabling of interrupts.
- Fully synthesizable.
- Static synchronous design.
- Positive edge clocking and no internal tri-states.
- Scan test ready.
- Simple interface allows easy connection to microprocessor/microcontroller devices.
- Benefits
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- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's TIMER IP contains following
- The TIMER interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases.
- Lint, CDC, Synthesis, Simulation Scripts with waiver files.
- IP-XACT RDL generated address map.
- Firmware code and Linux driver package.
- Documentation contains User's Guide and Release notes.
