ETHERNET CYCLIC FEC core is compliant with IEEE Standard 802.3.2018 Ethernet specification.Through its compatibility, it provides a simple interface to a wide range of low-cost devices. ETHERNET CYCLIC FEC IIP is proven in FPGA environment.The host interface of the ETHERNET CYCLIC FEC can be simple interface or can be AHB,AHB-Lite,APB,AXI,AXI-Lite,Tilelink,OCP,VCI,Avalon,PLB,Wishbone or Custom protocol.
ETHERNET CYCLIC FEC IIP is supported natively in Verilog and VHDL
- Features
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- Compliant with ETHERNET specification.
- Supports Full IEEE Standard 802.3.2018 Ethernet cyclic FEC functionality.
- This FEC(Forward Error correction) methodology implements the (2112 , 2080) binary cyclic code is shortened from the cyclic Fire code (42987, 42955).
- Supports FEC of 32 bits parity bits.
- This FEC can correct up to 11-bit burst error.
- Supports the pipelined mechanism for the error correction.
- Benefits
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- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs,license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's ETHERNET CYCLIC FEC IP contains following
- The ETHERNET CYCLIC FEC interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases.
- Lint, CDC, Synthesis, Simulation Scripts with waiver files.
- IP-XACT RDL generated address map.
- Firmware code and Linux driver package.
- Documentation contains User's Guide and Release notes.
