eSPI Slave is full-featured, easy-to-use, synthesizable design, compatible with standard protocol of standard eSPI specification.Through its eSPI compatibility,it provides a simple interface to a wide range of low-cost devices.eSPI Slave IIP is proven in FPGA environment.The host interface of the eSPI Slave can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite,AMBA AXI,AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink,Wishbone or Custom protocol.
eSPI Slave IIP is supported natively in Verilog and VHDL
- Features
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- Compliant with eSPI base specification as defined in Enhanced Serial Peripheral Interface (eSPI) Specification rev.1.0
- Supports Single, Dual and Quad modes
- Supports below transaction phases
- Command Phase
- Turn-Around Phase
- Response Phase
- Supports Slave triggered transaction
- Supports Power management Event
- Supports Interrupts and Alert
- Supports TX and RX operations as per specs
- Supports below multiple channels
- Peripheral Channel
- Virtual Wires Channel
- OOB Message (Tunneled SMBus) Channel
- Run-time Flash Access Channel
- Various kind of errors detection and handling
- Supports CRC checking
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to Microprocessor/Microcontroller
- Benefits
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- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's eSPI Slave IP contains following
- The eSPI Slave interface is available in Source and netlist products
- The Source product is delivered in verilog.If needed, VHDL and SystemC can also be provided
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and linux driver package
- Documentation contains User's Guide and Release notes
