Microwire Synthesizable Transactor provides a smart way to verify the MICROWIRE component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's MICROWIRE Serial Interface Synthesizable Transactor is fully compliant with standard MICROWIRE Specification and provides the following features.
- Features
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- Supports configurable address width from 2 to 32bit
- Supports configurable data width from 2 to 64bit
- Supports Master and Slave Mode
- Supports 3-wire interface
- Supports baud rate selection
- Supports internal clock division check
- Supports single and burst transfer mode
- Supports on the fly generation of data
- Supports Failchild, Microchip, Onsemi, ST EEPROM using microwire
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- Microwire Synthesizable Env
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SmartDV's Microwire Synthesizable env contains following:
- Synthesizable transactors
- Complete regression suite containing all the Microwire testcases
- Examples showing how to connect and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation also contains User's Guide and Release notes
