LPDDR3 DFI Verification IP provides an smart way to verify the LPDDR3 DFI component of a SOC or a ASIC. The SmartDV's LPDDR3 DFI Verification IP is fully compliant with standard DFI Specification and provides the following features.
LPDDR3 DFI Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
LPDDR3 DFI Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Compliant with DFI version 3.1 or higher Specifications.
- Supports LPDDR3 devices compliant with JEDEC LPDDR3 SDRAM Standard JESD209-3.pdf, JESD209-3B.pdf and JESD209-3C.pdf
- Supports for Read data-eye training
- Supports for Read gate training
- Supports for Write date-eye training
- Supports for CA training
- Supports for DFI disconnect during training
- Supports for write data mask and data strobe features.
- Supports for Power Down features.
- Supports for Deep Power Down features.
- Supports all data rates as per specification.
- Supports for Burst sequence.
- Supports for input clock stop and frequency change.
- Supports for Write leveling.
- Supports for X16 and X32 mode.
- Supports DRAM Clock disabling feature.
- Supports Error signaling.
- Supports Independent Operation & Multi-Configuration Support for LPDDR3.
- Supports all types of timing and protocol violations detection for timing parameters.
- Constantly monitors DFI behavior during simulation.
- Protocol checker fully compliant with DFI 3.1 or higher Specifications.
- Bus-accurate timing for min, max and typical values.
- Notifies the test bench of significant events such as transactions, warnings.
- Built in functional coverage analysis.
- Supports callbacks, so that user can access the data observed by monitor.
- Benefits
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- Faster test bench development and more complete verification of LPDDR3 DFI designs.
- Easy to use command interface simplifies monitor control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
- LPDDR3 DFI Verification Env
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SmartDV's LPDDR3 DFI Verification env contains following.
- Complete regression suite containing all the LPDDR3 DFI testcases.
- Complete UVM/OVM sequence library for LPDDR3 DFI controller.
- Examples showing how to connect and usage of Model.
- Detailed documentation of all classes, tasks and functions used in verification env.
- Documentation also contains User's Guide and Release notes.
