MIPI RFFE Post Silicon Validation IP provides a smart way to post silicon validation of the MIPI RFFE component of a SOC. MIPI RFFE Post Silicon Validation IP provides an smart way to post silicon validation of the MIPI RFFE bi-directional two-wire bus. The SmartDV's MIPI RFFE Post Silicon Validation IP is fully compliant with version 1.0,2.0,2.1 MIPI Alliance specification for RF Front-End Control Interface and provides the following features.
MIPI RFFE PSVIP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
MIPI RFFE PSVIP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Supports 1.0,2.0 and 2.1 MIPI RFFE Specification.
- Supports Full MIPI RFFE Master and Slave functionality.
- Operates as a Master, Slave, or both.
- Supports all topologies as per the MIPI RFFE specification.
- Supports multiple slaves.
- Supports following frames
- Command Frame
- Data/Address Frame
- No Response Frame
- Bus ownership transfer
- Interrupt polling
- Master write and read
- Master context write and context read
- Supports various kind of Master and Slave errors generation
- Undefined command frame
- Command frame with parity error
- Command frame legth error
- Address frame with parity error
- Data frame with parity error
- Read of unused register
- Write of an unused register
- Read using the broadcast ID or a GSID
- Various errors in Bus ownership transfer
- Supports extended register read/writes.
- Supports interrupt summary and identification command sequence.
- Supports Master ownership handover.
- Support Master write and read sequence.
- Supports device enumeration.
- Supports low power testing.
- Supports bus-accurate timing.
- Supports programmable speed.
- Benefits
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- Runs in custom FPGA platforms
- Validate RFFE device for compliance
- MIPI RFFE Post Silicon Validation IP Env
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SmartDV's MIPI RFFE Post Silicon Validation IP env contains following.
- Linux Perl Driver to control the PSVIP
- Encrypted RTL of PSVIP or Bit file for selected FPGA platform
- Complete regression suite containing all the MIPI RFFE testcases
- Detailed documentation of all functions of perl driver and testcases
- Documentation also contains User's Guide and Release notes
