RERAM Memory Model provides an smart way to verify the RERAM component of a SOC or a ASIC. The SmartDV's RERAM memory model is fully compliant with standard RERAM Specification and provides the following features. Better than Denali Memory Models.
RERAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
RERAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Supports RERAM memory devices from all leading vendors.
- Supports 100% of RERAM protocol standard.
- Supports all the RERAM commands as per the specs.
- Supports Serial peripheral Interface (SPI).
- Supports data retention without using a back-up battery.
- Supports upto 4 Mbits (524,288 Words x 8bits).
- Supports 1.2 x 10^6 rewrite operations.
- Supports 256 bytes write buffer size.
- Supports resistive-variable Memory.
- Supports up to 5 MHz (Max) Operating frequency.
- Supports Data endurance up to 1.2 x 10^6 times/byte.
- Supports Data retention up to 10 years.
- Supports WIP Polling.
- Supports Block Protection.
- Supports for all types of timing and protocol violation detection.
- Protocol checker fully compliant with RERAM Specification.
- Constantly monitors RERAM behavior during simulation.
- Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
- Built in functional coverage analysis.
- Supports Callbacks, so that user can access the data observed by monitor.
- Benefits
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- Faster testbench development and more complete verification of RERAM designs.
- Easy to use command interface simplifies monitor control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
- RERAM Verification Env
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SmartDV's RERAM Verification env contains following.
- Complete regression suite containing all the RERAM testcases.
- Examples showing how to connect and usage of Model.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
