100BASE-T1 Verification IP is compliant with IEEE 802.3 Specification and verifies MAC-to-PHY and PHY-to-MAC layer interfaces of designs with a 100BASE-T1 interface. It can work with SystemVerilog, Vera, SystemC, E and Verilog HDL environment.100BASE-T1 verification IP is developed by experts in Ethernet, who have developed ethernet products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a ethernet product.
100BASE-T1 Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
100BASE-T1 Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Supports 100BASE-T1 as per 802.3.bw
- Supports 4b/3b encoding
- Supports scrambler
- Supports 3b2T symbol mapping
- Supports PAM3 encoding scheme
- Supports MDIO slave and master model as per Clause 22 and Clause 45
- Supports 100M
- Supports MII
- Supports SMII as per specification 2.1
- Supports RMII as per specification 1.2
- Supports RGMII as per specification 2.0
- Supports SGMII as per specification 1.8
- Supports G.999.1 Interface
- 100BASE-T1 Verification IP comes with complete UNH Test suite
- Supports the following Upper layer protocols:
- IPV4
- IPV6
- TCP
- UDP
- ICMP
- ARP
- GRE
- NVGRE
- VXLAN
- PPPOE
- EAPoL
- FCOE
- RARP
- IPsec
- MACSEC
- Wake on LAN
- Slow protocol
- Supports IP in IP
- Supports Q in Q
- Supports Glitch insertion and detection
- Supports all types of TX and RX errors insertion/detection at each layer.
- Under and oversize frame.
- CRC errors
- Framing errors
- Pause frame errors
- Disparity and Auto-negotiation errors
- Invalid code group insertion
- Invalid /K/ characters insertion
- Lane Skew insertion
- Invalid AN sequence error insertion
- Missing /K/ characters for packet boundries.
- Comes with Tx BFM, Rx BFM, and Monitor
- Monitor supports detection of all protocol violations
- Supports Pause frame generation and detection
- Built in coverage analysis
- Callbacks in master and slave for various events
- Status counters for various events in bus
- Benefits
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- Faster testbench development and more complete verification of 100BASE-T1 designs.
- Easy to use command interface simplifies testbench control and configuration of 100BASE-T1 TX and RX.
- Simplifies results analysis.
- Runs in every major simulation environment.
- 100BASE-T1 Verification Env
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SmartDV's 100BASE-T1 Verification env contains following.
- Complete regression suite containing all the testcases.
- Examples showing how to connect various components, and usage of TX,RX BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
