SGPIO Initiator is full-featured, easy-to-use, synthesizable design, compatible with SFF-8485 Specification for Serial GPIO (SGPIO) Bus revision 0.7. Through its SGPIO Initiator compatibility, it provides a simple interface to a wide range of low-cost devices. SGPIO Initiator IIP is proven in FPGA environment. The host interface of the SGPIO Initiator can be simple interface or can be AMBA APB, AMBA AHB, AMBA AHB-Lite,AMBA AXI,AMBA AXI-Lite, VCI, OCP, Avalon, PLB, Tilelink,Wishbone or Custom protocol.
SGPIO Initiator IIP is supported natively in Verilog and VHDL
- Features
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- Compliant with SFF-8485 Specification for Serial GPIO (SGPIO) Bus revision 0.7
- Supports upto 256 hard disks
- Supports various operating frequency from 32Hz to 100KHz
- Supports to control High time and Low time of SGPIO Clock
- Supports transmit on rising edge and sample on falling edge
- Supports SGPIO LOAD to 0, when not exchanging a bit stream
- Supports SGPIO LOAD to 1, when SGPIO bus is not used
- Supports two blink generators A and B, used to control the output patterns
- Support two different modes
- Normal Mode
- General Purpose Mode
- Supports below different types of registers,
- Configuration registers
- Receive registers
- General purpose receive registers
- Transmit registers
- General purpose transmit registers
- Various kind of errors detection and interrupt handling
- Fully synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple interface allows easy connection to Microprocessor/Microcontroller devices
- Benefits
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- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's SGPIO Initiator IP contains following
- The SGPIO Initiator interface is available in Source and netlist products.
- The Source product is delivered in verilog.If needed, VHDL and SystemC can also be provided
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and linux driver package
- Documentation contains User's Guide and Release notes.
