HyperBus Synthesizable Transactor provides a smart way to verify the HyperBus component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's HyperBus Synthesizable Transactor is fully compliant with Cypress HyperBus Specification and provides the following features.
- Features
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- Supports HyperBus memory devices from all leading vendors.
- Supports 100% Cypress HyperBus specification standard.
- Supports all the HyperBus commands as per the specs.
- Supports 512 Mb HyperFlash and 64 Mb HyperRAM.
- Supports 8-bit data bus (DQ[7:0])
- Supports Read-Write Data Strobe (RWDS)
- Supports Device Identification Registers.
- Supports Configuration Registers.
- Supports Double-Data Rate(DDR) - two data transfers per clock.
- Supports Sequential burst transactions.
- Supports following Configurable burst characteristics.
- Wrapped burst length options
- 128 Bytes (64 clocks)
- 64 Bytes (32 clocks)
- 32 Bytes (16 clocks)
- 16 Bytes (8 clocks)
- Linear burst
- Hybrid option - one wrapped burst followed by linear burst
- Wrapped or linear burst type selected in each transaction
- Supports Configurable output drive strength.
- Checks for following
- Check-points include power up,initialization and power off rules
- State based rules
- All timing violations
- Supports following Power Conservation Modes.
- Interface Standby
- Active Clock Stop
- Deep Power-Down
- HyperFlash supports following features
- 512-byte Program Buffer
- Sector Erase
- Uniform 256-kB sectors
- Optional Eight 4-kB Parameter Sectors(32kB total)
- Advanced Sector Protection
- Volatile and non-volatile protection method for each sectors
- Separate 1024-byte one-time program array
- ECC 1-bit correction, 2-bit detection
- CRC (Check-value Calculation)
- Supports all types of timing and protocol violation detection.
- Protocol checker fully compliant with Cypress HyperBus Specification.
- Models, detects and notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- HyperBus Synthesizable Transactor Env
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SmartDV's HyperBus Synthesizable Transactor env contains following:
- Synthesizable transactors
- Complete regression suite containing all the HyperBus testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes
