I2C Synthesizable Transactor provides a smart way to verify the I2C component of a SOC or a ASIC in Emulator or FPGA platform. I2C Synthesizable Transactor provides an smart way to verify the I2C bi-directional two-wire bus. The SmartDV's I2C Synthesizable Transactor is fully compliant with version 6.0 of the Philip's I2C-Bus Specification and provides the following features.
- Features
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- Supports 6.0 I2C Specification
- Supports standard, fast, fast mode plus and high speed operations
- Supports full I2C Master and Slave functionality
- Operates as a Master, Slave, or both
- Start, repeat start and stop for all possible transfers
- Supports all I2C clocking speeds
- Supports 7b/10b configurable slave address
- Allows testing of various bus traffic for Read, Write, General Call and CBUS
- Supports bus arbitration for multi master
- Supports multiple slaves
- Supports insertion of wait states by slave and master
- Supports complex sequence of 7/10 bit with repeated start command sequences
- Supports Bus-accurate timing
- Supports START byte generation and handling
- Supports Master/Slave arbitration and clock synchronization
- Supports Glitch insertion and detection
- Supports AT24C1024 EEPROM memory model which supports 256 bytes Page Write Mode
- Supports Random and Sequential Read Modes
- Supports injection of various of errors
- Master aborting in middle of access
- Master doing ACK on last read access
- Master continues after NACK from slave for write data
- Random and Periodic clock period stretching by Slave
- Random Write NACK insertion by Slave
- Undersize/Oversize error
- Glitch injection on clock and data at various windows
- Compares read data with expected results
- Supports various kind of Master and Slave errors generation
- Notifies the testbench of significant events such as transactions, warnings, timing and protocol violations
- Status counters for various events in bus
- I2C Synthesizable Transactor comes with complete testsuite to test every feature of I2C specification
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- I2C Synthesizable Env
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SmartDV's I2C Synthesizable env contains following:
- Synthesizable transactor
- Complete regression suite containing all the I2C testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation contains User's Guide and Release notes
