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HDCP 1.x Transmitter IIP

HDCP 1.x Transmitter IIP

HDCP 1.x Transmitter core is compliant with standard HDCP specification as 1.3 and 1.4. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. HDCP 1.x Transmitter IIP is proven in FPGA environment. The Transmitter interface of the HDCP can be simple interface or can be AMBA APB, AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.

HDCP 1.x Transmitter IIP is supported natively in Verilog and VHDL

Features
  • Supports HDCP version 1.3 and 1.4 Specifications.
  • Supports full HDCP Transmitter functionality.
  • Fully synthesizable.
  • Static synchronous design.
  • Positive edge clocking and no internal tri-states.
  • Scan test ready.
  • Simple interface allows easy connection to microprocessor/microcontroller devices.
  • Supports HDCP Transmitter functionality for Display Port, HDMI and MHL content interfaces.
  • User keys can be loaded for Authentication.
  • Supports 8/16/24/32 bit width cipher output.
  • Supports Authentication Protocol.
  • Supports Encryption Status Signaling.
    • Enhanced Encryption Status Signaling (EESS).
    • Original Encryption Status Signaling (OESS).
  • Supports System Renewability Message (SRM) and Revocation.
  • Supports SHA-1 Algorithm for Authentication.
  • Supports HDCP RNG functionality.
Benefits
  • Single site license option is provided to companies designing in a single site.
  • Multi sites license option is provided to companies designing in multiple sites.
  • Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
  • Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
Deliverables

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    SmartDV's HDCP 1.x Transmitter IP contains following

  • The HDCP 1.x Transmitter interface is available in Source and netlist products.
  • The Source product is delivered in plain text verilog. If needed VHDL,SystemC code can also be provided.
  • Easy to use Verilog Test Environment with Verilog Testcases
  • Lint, CDC, Synthesis, Simulation Scripts with waiver files
  • IP-XACT RDL generated address map
  • Firmware code and Linux driver package
  • Documentation contains User's Guide and Release notes.

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