AMBA AXI4-Stream Assertion IP provides an smart way to verify the ARM AMBA AXI4-Stream component of a SOC or a ASIC. The SmartDV's AMBA AXI4-Stream Assertion IP is fully compliant with standard AMBA AXI4-Stream Specification and provides the following features.
AMBA AXI4-Stream Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
AMBA AXI4-Stream Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Specification Compliance
- Compliant with the latest ARM AMBA AXI4-Stream Protocol Specification.
- Supports all AXI4-Stream data widths.
- Support for all Data streams including Byte stream, Continuous aligned stream, Continuous unaligned stream and Sparse stream.
- Support for single byte, packet and frame transfers.
- Transfer interleaving support.
- Ability to configure the width of all signals.
- Support for bus inactivity detection and timeout
- Assertion IP features
- Assertion IP includes:
- System Verilog assertions
- System Verilog assumptions
- System Verilog cover properties
- Synthesizable Verilog Auxiliary code
- Support Master mode, Slave mode, Monitor mode and Constraint mode.
- Supports Simulation mode (stimulus from SmartDV AXI4-Stream VIP) and Formal mode (stimulus from Formal tool).
- Rich set of parameters to configure AXI4-Stream Assertion IP functionality.
- Benefits
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- Runs in every major formal and simulation environment.
- AMBA AXI4-Stream Assertion Env
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SmartDV's AMBA AXI4-Stream Assertion env contains following.
- Detailed documentation of Assertion IP usage.
- Documentation also contains User's Guide and Release notes.
