HBM3 Synthesizable Transactor provides a smart way to verify the HBM3 component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's HBM3 Synthesizable Transactor is fully compliant with HBM3 draft Specification and provides the following features.
- Features
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- Supports 100% of HBM3 protocol draft JEDEC specification version 1.1.
- Supports all the HBM3 commands as per the specs.
- Supports programmable clock frequency of operation.
- Support all types of timing and protocol violation detection.
- Supports burst length 8.
- Supports programmable READ/WRITE Latency timings.
- Supports Bank grouping.
- Supports 16, 32 or 48 banks per channel based on device density and channel.
- Supports 2KB page size per channel.
- Supports up to 16 channels per stack.
- Supports semi-independent row and column command interfaces.
- Supports WDQS-to-CK training.
- Checks for following
- Check-points include power on, Initialization and power off rules,
- State based rules, Active Command rules,
- Read/Write Commands rules etc.
- All timing violations.
- Supports all Mode registers programming.
- Supports DBIac write and read.
- Supports Pseudo Channel Mode Operation (32 DQ width for Pseudo Channel Mode).
- Supports 2 Pseudo channels per channel.
- Supports Self-Refresh Modes.
- Supports IEEE standard 1500.
- Supports channel density of 2 GB to 32 GB.
- Supports 64 DQ width + Optional ECC pin support/channel.
- Supports write data mask and data strobe features.
- Supports power down features.
- Supports input clock stop and frequency change.
- Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
- Protocol checker fully compliant with HBM3 JEDEC draft specification version 1.1.
- Models, detects and notifies the test bench of significant events such as transactions, warnings, timings and protocol violations.
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- HBM3 Synthesizable Transactor Env
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SmartDV's HBM3 Synthesizable Transactor env contains following:
- Synthesizable transactors
- Complete regression suite containing all the HBM3 testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and function's used in verification env
- Documentation contains User's Guide and Release notes
