LDPC (1723,2048) core is compliant with IEEE Standard 802.3.2018 Ethernet specification. Through its compatibility, it provides a simple interface to a wide range of low-cost devices. LDPC (1723,2048) IIP is proven in FPGA environment. The host interface of the LDPC (1723,2048) can be simple interface or can be AHB, AHB-Lite, APB, AXI, AXI-Lite, Tilelink, OCP, VCI, Avalon, PLB, Wishbone or custom buses.
LDPC (1723,2048) IIP is supported natively in Verilog and VHDL
- Features
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- Compliant with IEEE Standard 802.3.2018 Ethernet specification.
- Supports full LDPC functionality.
- Supports the Lower density parity check (1723,2048).
- Supports the parity generation of 325 bits.
- Supports the bit locker mechanism.
- Supports the parity checking.
- Supports the syndrome calculation.
- Supports the error correction mechanism.
- Supports the pipe-lined mechanism for the error correction.
- Benefits
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- Single site license option is provided to companies designing in a single site.
- Multi sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's LDPC (1723,2048) IP contains following
- The LDPC (1723,2048) interface is available in Source and netlist products.
- The Source product is delivered in plain text verilog.If needed VHDL,SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
