Excelon FRAM Memory Model provides an smart way to verify the Excelon FRAM component of a SOC or a ASIC. The SmartDV's Excelon FRAM memory model is fully compliant with standard Excelon FRAM Specification and provides the following features. Better than Denali Memory Models.
Excelon FRAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
Excelon FRAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
-
- Supports Excelon FRAM memory devices from all leading vendors.
- Supports 100% of Excelon FRAM protocol standard CY15B104QN, CY15B108QN, CY15B102QN, CY15B104QI, CY15B104QSN, CY15B108QI.
- Supports all the Excelon FRAM commands as per the specs.
- Quickly validates the implementation of the Excelon FRAM standard CY15B104QN, CY15B108QN, CY15B102QN, CY15B104QI, CY15B104QSN, CY15B108QI.
- Supports for 4-Mbit ferroelectric random access memory (F-RAM) logically organized as 512K×8
- Supports for 8-Mbit ferroelectric random access memory (F-RAM) logically organized as 1024K×8
- Supports for 2-Mbit ferroelectric random access memory (F-RAM) logically organized as 256K×8
- Supports for Fast serial peripheral interface (SPI)
- Supports for Device ID and Serial Number
- Device ID includes manufacturer ID and product ID
- Unique ID
- Serial Number
- Supports for Sophisticated write protection scheme
- Hardware protection using the Write Protect (WP) pin
- Software protection using Write Disable (WRDI) instruction
- Software block protection for 1/4, 1/2, or entire array
- Supports for Dedicated 256-byte special sector F-RAM
- Dedicated special sector write and read
- Content can survive up to three standard reflow cycles
- Supports programmable clock frequency of operation.
- Supports for all types of timing and protocol violation detection.
- Checks for following
- Check-points include power on, Initialization and power off rules,
- State based rules, Active Command rules,
- Read/Write Command rules etc.
- All timing violations.
- Constantly monitors Excelon FRAM behavior during simulation.
- Supports Protocol checker fully compliant with Excelon FRAM Specification CY15B104QN, CY15B108QN, CY15B102QN, CY15B104QI, CY15B104QSN, CY15B108QI.
- Notifies the test bench of significant events such as transactions, warnings, timing and protocol violations.
- Built in functional coverage analysis.
- Supports Callbacks, so that user can access the data observed by monitor.
- Benefits
-
- Faster testbench development and more complete verification of Excelon FRAM designs.
- Easy to use command interface simplifies monitor control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
- Excelon FRAM Verification Env
-
SmartDV's Excelon FRAM Verification env contains following.
- Complete regression suite containing all the Excelon FRAM testcases.
- Complete UVM/OVM sequence library for Excelon FRAM controller.
- Examples showing how to connect and usage of Model.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
