MRAM Memory Model provides an smart way to verify the MRAM component of a SOC or a ASIC. The SmartDV's MRAM memory model is fully compliant with standard MRAM Specification and provides the following features. Better than Denali Memory Models.
MRAM Memory Model is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
MRAM Memory Model comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Supports MRAM memory devices from all leading vendors.
- Supports 100% of MRAM protocol standard.
- Supports all the MRAM commands as per the MR2A16A and MR0A08B specifications
- Supports Symmetrical high-speed read and write with fast access time.
- Supports SRAM Compatible timing
- Supports native non-volatility
- Supports Unlimited read and write endurance
- Supports highly reliable data storage
- Supports the following operating modes
- Byte read
- Byte write
- Output Disabled
- Not Selected
- Quickly validates the implementation of the MRAM standard MR2A16A and MR0A08B.
- Supports Flexible data bus control - 8 bit or 16 bit access.
- Supports Flexible density of 4Mb or 16Mb
- Checks for following
- Check-points include power up, initialization and power off rules
- Read/Write byte Command rules etc.,
- All timing violations
- Supports all types of timing and protocol violation detection..
- Protocol checker fully compliant with MRAM Specifications MR2A16A and MR0A08B.
- Constantly monitors MRAM behavior during simulation.
- Protocol checker fully compliant with MRAM Specification.
- Models, detects and notifies the test bench of significant events such as transactions, warnings, and timing and protocol violations.
- Built in functional coverage analysis.
- Supports Callbacks, so that user can access the data observed by monitor
- Benefits
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- Faster testbench development and more complete verification of MRAM designs.
- Easy to use command interface simplifies monitor control and configuration.
- Simplifies results analysis.
- Runs in every major simulation environment.
- MRAM Verification Env
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SmartDV's MRAM Verification env contains following.
- Complete regression suite containing all the MRAM testcases.
- Complete UVM/OVM sequence library for MRAM controller.
- Examples showing how to connect and usage of Model.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
