LPDDR5 Assertion IP provides an efficient and smart way to verify the LPDDR5 designs quickly without a testbench. The SmartDV's LPDDR5 Assertion IP is fully compliant with standard LPDDR5 Specification JESD209-5, JESD209-5A and JESD209-5B.
LPDDR5 Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
LPDDR5 Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Specification Compliance
- Supports 100% of LPDDR5 protocol standard JESD209-5, JESD209-5A and JESD209-5B.
- Supports all the LPDDR5 commands as per the specs
- Supports 2:1 and 4:1 CKR mode.
- Supports X8 and X16 device modes.
- Supports WCK2CK Sync operation
- Supports burst length 16 and 32
- Supports for all mode registers programming
- Supports Read DBI and Write DBI operation
- Supports for Hybrid Refresh mode and Refresh credit mode
- Supports for Write zero CAS command
- Supports all data rates as per specification
- Checks for following
- Check-points include power on, Initialization and power off rules,
- State based rules, Active Command rules,
- Read/Write Command rules etc,
- All timing violations
- Supports deep sleep mode
- Supports power down mode and refresh operation
- Supports power down mode and self-refresh operation.
- Supports CA parity and ECC.
- Quickly validates the implementation of the standard JESD209-5, JESD209-5A and JESD209-5B specification
- Bus-accurate timing for min, max and typical values
- Constantly monitors LPDDR5 behavior
- Protocol Checker fully compliant with LPDDR5 Specification JESD209-5, JESD209-5A and JESD209-5B.
- Assertion IP features
- Assertion IP includes:
- System Verilog assertions
- System Verilog assumptions
- System Verilog cover properties
- Synthesizable Verilog Auxiliary code
- Support Master mode, Slave mode, Monitor mode and Constraint mode
- Supports Simulation mode (stimulus from SmartDV LPDDR5 VIP) and Formal mode (stimulus from Formal tool)
- Rich set of parameters to configure LPDDR5 Assertion IP functionality
- Benefits
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- Runs in every major formal and simulation environment.
- LPDDR5 Assertion Env
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SmartDV's LPDDR5 Assertion env contains following.
- Detailed documentation of Assertion IP usage.
- Documentation also contains User's Guide and Release notes.
