HBM Assertion IP provides an efficient and smart way to verify the HBM designs quickly without a testbench. The SmartDV's HBM Assertion IP is fully compliant with standard HBM Specification.
HBM Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
HBM Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Specification Compliance
- Supports HBM memory devices from all leading vendors.
- Supports 100% of HBM protocol standard JESD235, JESD235A, JESD235B, JESD235C and JESD235D.
- Supports all the HBM commands as per the specs.
- Supports all types of timing and protocol violation detection.
- Supports burst length of 2 and 4.
- Supports programmable Read/Write latency timings.
- Supports bank grouping.
- Supports 8, 16, 32, 48 and 64 banks per channel.
- Supports up to 8 channels per stack.
- Supports Extended Addressing.
- Supports Extended Write latency and read latency.
- Checks for following
- Check-points include power on, initialization and power off rules,
- State based rules, active command rules,
- Read/Write commands rules etc.
- All timing violations.
- Supports all mode registers programming.
- Supports DBIac write and read.
- Supports legacy mode and pseudo channel mode operation (64 DQ width for pseudo channel mode).
- Supports self-refresh modes.
- Supports channel density of 1 GB to 128 GB.
- Supports 128 DQ width + optional ECC pin support/channel.
- Supports ECC.
- Supports write data mask and data strobe features.
- Supports for power down features.
- Supports for target row refresh mode.
- Supports for temperature compensated refresh reporting.
- Supports for IEEE standard 1500.
- Bus-accurate timing for min, max and typical values.
- Constantly monitors HBM behavior during simulation.
- Protocol checker fully compliant with HBM specification JESD235, JESD235A,JESD235B, JESD235C and JESD235D.
- Assertion IP features
- Assertion IP includes:
- System Verilog assertions
- System Verilog assumptions
- System Verilog cover properties
- Synthesizable Verilog Auxiliary code
- Support Master mode, Slave mode, Monitor mode and Constraint mode.
- Supports Simulation mode (stimulus from SmartDV HBM VIP) and Formal mode (stimulus from Formal tool).
- Rich set of parameters to configure HBM Assertion IP functionality.
- Benefits
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- Runs in every major formal and simulation environment.
- HBM Assertion Env
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SmartDV's HBM Assertion env contains following.
- Detailed documentation of Assertion IP usage.
- Documentation also contains User's Guide and Release notes.
