LIN Synthesizable Transactor provides a smart way to verify the LIN component of a SOC or a ASIC in Emulator or FPGA platform. Local Interconnect Network (LIN) Synthesizable Transactor is a single-wire, serial communication protocol based on the UART interface that is gaining popularity as a sub-bus standard in the automotive industry. LIN Transactor are reusable components that provide ready made verification environment. Compatible with Local Interconnect Network (LIN) specifications version 2.2A and supports all the frame types such as Unconditional, Event-triggered, Sporadic, Diagnostic and Reserved frames.
LIN 2.2A Synthesizable Transactor includes an extensive test suite covering most of the possible scenarios. It can perform all protocal tests and moreover it allows an easy generation of very high number of patterns and a set of specified patterns to stress the DUT.
- Features
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- Compatible with Local Interconnect Network (LIN) specifications version 2.2A
- Compliant with ISO/DIS 17987-2, ISO/DIS 17987-3 and ISO/DIS 17987-4
- Supports test cases as per standard
- INTERNATIONAL STANDARD ISO/DIS 17987-6
- Supports Unconditional, Event- triggered, Sporadic and Diagnostic frames
- Unconditional frames
- Event-triggered frames
- Sporadic frames
- Diagnostics frames
- Reserved frames
- Supports programmable clock frequency of operation
- Simulates LIN cluster with number of nodes the user requires
- These LIN nodes can be configured as Master or Slave nodes
- The DUT can either be a LIN 2.2A master or slave device
- Supports cluster wake up and go to sleep
- Supports all types of error insertion and detection
- Checksum error
- Parity error
- Oversize error
- PID start/stop error
- Sync start/stop error
- Break length error
- Delimiter error
- Diagnostic frame errors
- Supports glitch insertion and detection
- Benefits
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- Compatible with testbench writing using SmartDV's VIP
- All UVM sequences/testcases written with VIP can be reused
- Runs in every major emulators environment
- Runs in custom FPGA platforms
- LIN Synthesizable Env
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SmartDV's LIN Synthesizable env contains following
- Synthesizable transactors
- Complete regression suite containing all the LIN testcases
- Examples showing how to connect various components, and usage of Synthesizable Transactor
- Detailed documentation of all DPI, class, task and functions used in verification env
- Documentation contains User's Guide and Release notes
