DFI HBM Assertion IP provides an efficient and smart way to verify the DFI HBM designs quickly without a testbench. The SmartDV's DFI HBM Assertion IP is fully complian with standard DFI HBM Specification.
HBM DFI Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
HBM DFI Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Specification Compliance
- Compliant with DFI version 4.0 or 5.0 Specifications.
- Supports HBM devices compliant with JEDEC HBM DRAM Standard JESD235, JESD235A, JESD235B and JESD235C.
- Supports all Interface Groups.
- Supports Write Transactions with Data mask
- Supports DRAM Clock disabling feature.
- Supports Data bit enable/disable feature.
- Supports 1:1, 1:2 and 1:4 MC to PHY frequency ratio.
- Supports frequency change protocol.
- Supports Low power control features.
- Supports Error signaling.
- Supports DFI Read/Write Chip Select.
- Supports all types of timing and protocol violations detection for timing parameters like tphy_wrlat ,tphy_wrdata,trd_dataen and tphy_rdlat delays
- Constantly monitors DFI behavior during simulation.
- Protocol checker fully compliant with DFI 4.0 or 5.0 Specifications.
- Assertion IP features
- Assertion IP includes:
- System Verilog assertions
- System Verilog assumptions
- System Verilog cover properties
- Synthesizable Verilog Auxiliary code
- Support Master mode, Slave mode, Monitor mode and Constraint mode.
- Supports Simulation mode (stimulus from SmartDV HBM VIP) and Formal mode (stimulus from Formal tool).
- Rich set of parameters to configure HBM Assertion IP functionality.
- Benefits
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- Runs in every major formal and simulation environment.
- HBM Assertion Env
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SmartDV's HBM Assertion env contains following.
- Detailed documentation of Assertion IP usage.
- Documentation also contains User's Guide and Release notes.
