The 100GBase-KR10/CR10/SR10/LR4 Ethernet Verification IP is compliant with IEEE 802.3ba specifications and verifies MAC-to-PHY layer interfaces of designs with a 100G Ethernet interface 100GBase-KR10/CR10/SR10/LR4. It can work with SystemVerilog, Vera, SystemC, E and Verilog HDL environment. 100GBase-KR10/CR10/SR10/LR4 verification IP is developed by experts in Ethernet, who have developed ethernet products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a ethernet product.
100GBase-KR10/CR10/SR10/LR4 Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
100GBase-KR10/CR10/SR10/LR4 Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Supports 100GBase-KR10/CR10/SR10/LR4 interface as per the specification defined in IEEE 802.3ba
- Supports scrambler
- Supports FEC
- Supports backplane auto-negotation
- Supports 100GBASE-KP4 with PMA enable.
- Supports Gray coding and Precoding as per Spec IEEE 802.3
- Supports CDR for serial protocols
- Supports MDIO slave and master model as per Clause 22 and Clause 45
- Supports Glitch insertion and detection
- Supports Pause frame generation and detection.
- Supports all types of 100GBase-KR10/CR10/SR10/LR4 TX and RX errors insertion/detection.
- Oversize, undersize, inrange, out of range Packet size errors
- Missing SPD/EPD/SFD framing errors
- SFD on wrong lane
- CRC Error
- Lane skew insertion
- Disparity error injection
- Invalid /D/ and /K/ character injection
- Variable preamble and IPG insertion
- Invalid block code insertion
- Sync bit corruption
- FEC error injection
- Scrambler error injection
- Comes with 100GBase-KR10/CR10/SR10/LR4 Tx BFM, 100GBase-KR10/CR10/SR10/LR4 Rx BFM, and 100GBase-KR10/CR10/SR10/LR4 PCS Monitor
- Monitor supports detection of all protocol violations.
- Built in coverage analysis.
- Benefits
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- Faster testbench development and more complete verification of 100GBase-KR10/CR10/SR10/LR4 designs.
- Easy to use command interface simplifies testbench control and configuration of 100GBase-KR10/CR10/SR10/LR4 TX and RX.
- Simplifies results analysis.
- Runs in every major simulation environment.
- 100GBase-KR10/CR10/SR10/LR4 Verification Env
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SmartDV's 100GBase-KR10/CR10/SR10/LR4 Verification env contains following.
- Complete regression suite containing all the testcases.
- Examples showing how to connect various components, and usage of TXRX BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
