The 10G Ethernet Verification IP is compliant with IEEE 802.3 specifications and verifies MAC-to-PHY layer interfaces of designs with a 10G Ethernet interface XGMII. It can work with SystemVerilog,Vera, SystemC, E and Verilog HDL environment. GMII TBI verification IP is developed by experts in Ethernet, who have developed ethernet products in companies like Intel, Cortina-Systems, Emulex, Cisco. We know what it takes to verify a ethernet product.
XGMII Ethernet Verification IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
XGMII Ethernet Verification IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Follows XGMII specification as defined in IEEE 802.3
- Supports all types of XGMII TX and RX errors insertion/detection.
- Oversize, undersize, inrange, out of range Packet size errors
- Missing SPD/EPD/SFD framing errors
- SPD/SFD on wrong lane
- CRC Error
- Invalid /D/ and /K/ character injection
- Variable preamble and IPG insertion
- Supports sending and receiving of remote and local faults
- Comes with XGMII Tx BFM, XGMII Rx BFM, and XGMII Monitor
- Monitor supports detection of all protocol violations.
- Supports Pause frame generation and detection.
- Built in coverage analysis.
- Benefits
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- Faster testbench development and more complete verification of XGMII designs.
- Easy to use command interface simplifies testbench control and configuration of XGMII TX and RX.
- Simplifies results analysis.
- Runs in every major simulation environment.
- XGMII Verification Env
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SmartDV's XGMII Verification env contains following.
- Complete regression suite (UNH) containing all the XGMII testcases.
- Examples showing how to connect various components, and usage of TXRX BFM and Monitor.
- Detailed documentation of all class, task and function's used in verification env.
- Documentation also contains User's Guide and Release notes.
