• Home
  • About Us
    • Partners
    • Careers
  • Products
    • Verification IPs
      • MIPI Verification IPs
      • Networking and SOC Verification IPs
      • Automotive And Serial Bus Verification IPs
      • Storage And Video Verification IPs
    • Memory Models
      • DDR SDRAM Memory Models
      • DFI Verification IPs
      • DIMM Memory Models
      • Flash Memory Models
      • Graphics Memory Models
      • High Bandwidth Memory Models
      • Low Power Memory Models
      • Misc Memory Models
      • Non volatile Memory Models
      • SDRAM Memory Models
      • SRAM Memory Models
    • SimXL - Emulation Models
      • MIPI Synthesizable Transactors
      • Networking and SOC Synthesizable Transactors
      • Automotive And Serial Bus Synthesizable Transactors
      • Storage And Video Synthesizable Transactors
      • DDR SDRAM Memory Synthesizable Transactors
      • Low Power Memory Synthesizable Transactors
      • Graphics Memory Synthesizable Transactors
      • Flash Memory Synthesizable Transactors
      • High Bandwidth Memory Synthesizable Transactors
      • SDRAM Memory Synthesizable Transactors
      • SRAM Memory Synthesizable Transactors
      • Non volatile Memory Synthesizable Transactors
      • DIMM Memory Synthesizable Transactors
      • Misc Memory Synthesizable Transactors
      • DFI Synthesizable Transactors
    • Formal Verification IPs (Assertion IP)
      • Networking and SOC Assertion IPs
      • DDR SDRAM Memory Assertion IPs
      • Low Power Memory Assertion IPs
      • Graphics Memory Assertion IPs
      • High Bandwidth Memory Assertion IPs
      • SDRAM Memory Assertion IPs
      • DFI Assertion IPs
      • Serial Assertion IPs
    • Post Silicon Validation IPs
      • MIPI Post Silicon Validation IPs
    • Design IPs
      • DDR Controller Design IPs
      • Ethernet Design IPs
      • Serial Bus Design IPs
      • Audio Video Design IPs
      • MIPI Design IPs
      • Automotive Design IPs
      • Bridge Design IPs
      • DMA Controller Design IPs
      • Flash Controller Design IPs
      • High Speed Design IPs
  • Customers
  • News & Events
  • Support
  • Contact Us
Products

OCP Synthesizable Transactor

OCP Synthesizable Transactor

OCP Synthesizable Transactor provides a smart way to verify the OCP component of a SOC or a ASIC in Emulator or FPGA platform. The SmartDV's OCP Synthesizable Transactor is fully compliant with standard OCP Specification 3.1 and provides the following features

Features
  • Compliant with OCP 3.1 specification
  • Supports OCP Master, OCP Slave
  • Supports all OCP protocol transfer & command types
  • Supports all OCP protocol signal widths including address and data
  • Supports all OCP protocol burst models, burst lengths and response types
  • Supports SRMD and MRMD bursts
  • Ability to pipeline transfers and non-blocking flow control support
  • Supports concurrency and out-of-order processing of transfers
    • Multi-threading and tagging support
  • Supports Request interleaving
  • Master/Slave Connect-Disconnect feature support
  • Supports 2-Dimensional block burst address sequences
  • Compliance to phase-ordering rules
  • Complete support for full range of OCP configurations
  • Supports asynchronous/synchronous reset and EnableClk mechanism. On the fly reset control
  • Supports threadBusy behavior
  • Supports all sideband signals
  • Supports coherence extensions
  • Slave supports fine grain control of response per address or per transfer
  • Supports programmable timeout insertion
  • Supports on-the-fly protocol and data checking
Benefits
  • Compatible with testbench writing using SmartDV's VIP
  • All UVM sequences/testcases written with VIP can be reused
  • Runs in every major emulators environment
  • Runs in custom FPGA platforms
OCP Synthesizable Transactor Env

    Note: Only mails from offical mail ID will be processed

    Request Datasheet
    Request Evaluation

    SmartDV's OCP Synthesizable env contains following:

  • Synthesizable transactors
  • Complete regression suite containing all the OCP testcases
  • Examples showing how to connect various components, and usage of Synthesizable Transactor
  • Detailed documentation of all class, task and functions used in verification env
  • Documentation contains User's Guide and Release notes

About SmartDV
Partners
Careers
Products
Customers
News & Events

Verification IP
Memory Models
SimXL - Emulation Models
Formal Verification IP (Assertion IP)
Post-Silicon Validation IP
Design IP

info@smart-dv.com

Contact Us
Support

Copyright © SmartDV Technologies India Private Limited All rights reserved.