USB2.x Hub interface provides full support for the USB2.x synchronous serial interface, compatible with USB 2.0 specification. Through its USB2.x compatibility, it provides a simple interface to a wide range of low-cost devices. USB2.x Hub IIP is proven in FPGA environment. The host interface of the USB2.x Hub can be simple interface or can be AMBA AHB, AMBA AXI, VCI, OCP, Avalon, PLB, Tilelink, Wishbone or Custom protocol.
USB2.x HUB IIP is supported natively in Verilog and VHDL
- Features
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- Compliant with USB 2.0 Specification
- Supports High/Full speed using 8/16 bit UTMI/ULPI interface
- Supports Optional PIO Mode for each endpoint (can be used for Interrupt endpoints)
- Supports System bus Master/Target clock
- Supports Endpoint Configuration
- Configurable up to 15 downstream ports
- Supports Bulk/control/ isochronous/interrupt transfers
- Supports Dedicated control endpoint zero
- Supports Configurable dual port RAM shared between endpoints
- Supports USB Suspend/Resume support
- Supports LPM
- Support Remote wakeup
- Supports Shared TT for the downstream ports for HS/FS/LS
- Supports Downstream device connect/disconnect detection
- Supports HS Repeater for the downstream HS device
- Supports suspend and resume for power management
- Support link power management
- Supports test mode features.
- Various kind of errors detection and handling
- Supports CRC checking
- Fully Synthesizable
- Static synchronous design
- Positive edge clocking and no internal tri-states
- Scan test ready
- Simple Interface allows easy connection to microprocessor/microcontroller devices.
- This core achieves ASIL B and can be made to achieve ASIL D as per ISO26262
- Benefits
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- Single Site license option is provided to companies designing in a single site.
- Multi Sites license option is provided to companies designing in multiple sites.
- Single Design license allows implementation of the IP Core in a single FPGA bitstream and ASIC.
- Unlimited Designs, license allows implementation of the IP Core in unlimited number of FPGA bitstreams and ASIC designs.
- Deliverables
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SmartDV's USB2.x Hub IP contains following
- The USB2.x Hub interface is available in Source and netlist products.
- The Source product is delivered in verilog. If needed VHDL, SystemC code can also be provided.
- Easy to use Verilog Test Environment with Verilog Testcases
- Lint, CDC, Synthesis, Simulation Scripts with waiver files
- IP-XACT RDL generated address map
- Firmware code and Linux driver package
- Documentation contains User's Guide and Release notes.
- ISO26262 Safety Manual (SAM) Document
- ISO26262 Failure Modes, Effects and Diagnostics Analysis (FMEDA) Document
