I2C Assertion IP provides an efficient and smart way to verify the I2C designs quickly without a testbench. The SmartDV's I2C Assertion IP is fully compliant with standard I2C Specification.
I2C Assertion IP is supported natively in SystemVerilog, VMM, RVM, AVM, OVM, UVM, Verilog, SystemC, VERA, Specman E and non-standard verification env
I2C Assertion IP comes with optional Smart Visual Protocol Debugger (Smart ViPDebug), which is GUI based debugger to speed up debugging.
- Features
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- Specification Compliance
- Supports 6.0 I2C specifications.
- Start, repeat start and stop for all possible transfers.
- Supports all I2C clocking speeds including HS mode, Fast mode, Fast mode plus and Ultra-fast mode.
- 7b/10b configurable Slave address.
- Allows testing of various bus traffic for Read, Write, General Call and CBUS.
- Supports complex sequence of 7/10 bit with repeated start command sequences.
- Supports Bus-accurate timing.
- Assertion IP features
- Assertion IP includes:
- System Verilog assertions
- System Verilog assumptions
- System Verilog cover properties
- Synthesizable Verilog Auxiliary code
- Support Master mode, Slave mode, Monitor mode and Constraint mode.
- Supports Simulation mode (stimulus from SmartDV I2C VIP) and Formal mode (stimulus from Formal tool).
- Rich set of parameters to configure I2C Assertion IP functionality.
- Benefits
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- Runs in every major formal and simulation environment.
- I2C Assertion Env
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SmartDV's I2C Assertion env contains following.
- Detailed documentation of Assertion IP usage.
- Documentation also contains User's Guide and Release notes.
